Techniques to enable disaggregation of physical memory resources in a compute system

ABSTRACT

Various embodiments are generally directed to an apparatus, method and other techniques enable disaggregation of physical memory resources from physical compute resources. For example, embodiments may include a memory interface coupled with the memory controller and a memory module. The memory interface may receive data in parallel via a bus, and convert the received parallel data to send to a memory module of a memory expander sled in serial via a high speed serial link, and receive data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to the memory controller via the bus.

RELATED CASES

This application claims priority to U.S. Provisional Patent ApplicationNo. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent ApplicationNo. 62/376,859, filed Aug. 18, 2016, and U.S. Provisional PatentApplication No. 62/427,268, filed Nov. 29, 2016, each of which arehereby incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments described herein generally include determining andcommunicating metric for physical resources in a data centerenvironment.

BACKGROUND

A computing data center may include one or more computing systemsincluding a plurality of compute nodes or sleds that may include variouscompute structures and may be physically located on multiple racks.These sleds may include a number of physical resources and provideprocessing and storage capabilities.

From time-to-time these physical resources may need to be replaced andupdated due to failures and newer equipment. Typically, processingresources and memory resources on a sled are replaced at the same timebecause it is difficult to disaggregate the memory resources fromprocessing resources. This significantly increases the total cost ofmaintaining the data center since the cost of memory resources occupiesa large percentage of the total cost of a sled. Thus, embodiments aredirected to solving these others problem.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example, and notby way of limitation, in the figures of the accompanying drawings inwhich like reference numerals refer to similar elements.

FIG. 1 illustrates an example of a data center.

FIG. 2 illustrates an example of a rack.

FIG. 3 illustrates an example of a data center.

FIG. 4 illustrates an example of a data center.

FIG. 5 illustrates an example of a switching infrastructure.

FIG. 6 illustrates an example of a data center.

FIG. 7 illustrates an example of a sled.

FIG. 8 illustrates an example of a data center.

FIG. 9 illustrates an example of a data center.

FIG. 10 illustrates an example of a sled.

FIG. 11 illustrates an example of a data center.

FIG. 12 illustrates an example of a compute system.

FIG. 13 illustrates an example of a compute system.

FIG. 14 illustrates an example of a compute system.

FIG. 15 illustrates an example of logic flow diagrams.

FIG. 16 illustrates an example of logic flow diagrams.

FIG. 17 illustrates an example of a logic flow diagram.

DETAILED DESCRIPTION

Various embodiments may be generally directed to enabling disaggregationof physical compute resources from physical memory resources. Aspreviously discussed, physical compute resources, such as processors,and physical memory resources are typically replaced at the same timebecause of their integration on the same sled or node. Thus, embodimentsare directed to disaggregation solutions to decouple physical computeresources and physical memory resources such that when physical computeresources are replaced, the physical memory resources may be reused.Some of the solutions discussed herein may include physical memoryresources incorporated on a memory expander sled coupled with thephysical compute resources on a different sled via a high speed link.The memory expander sled may come in various form factors, such as thedual in-line memory module (DIMM) form factor or a solid state drive(SSD) form factor to reduce the overall size and footprint of the memoryexpander sled.

In one example, the physical memory resources may be implemented in amemory expander sled in a SSD form factor, as previously mentioned. Inthis example, the SSD form factor may enable a reduction in pin count,but maintain high speed serial links between the physical memoryresources and the physical compute resources.

In another example, the physical memory resources may be in a memoryexpander sled having DIMM form factor and coupled with the physicalcompute resources via a pig tail connector. The pig tail connector maycouple with the physical compute resources via a high serial speed linkand include circuitry to convert parallel data to serial data to senddata to the physical memory resources. The expander sled may alsoinclude circuitry to convert serial data back to parallel data at thephysical memory resources for communication with the memory modules.During read operations, the expander sled including the circuitry mayconvert data read from memory devices from parallel data to serial datato communicate to the physical compute resources via the high serialspeed link and pig tail connector. The pig tail connector may receivethe data and convert it from serial data back to parallel data tocommunicate to the physical compute resources. The parallel data may bedata communicated in parallel via a bus or link and the serial data maybe data communicated in serial via a bus or link.

In a third example, the physical memory resources may be incorporated ina memory expander sled, and asled including the physical computeresources may be coupled with the memory expander sled via a high speedserial link. In this example, the sled having the physical computeresources may have one or more memory controllers andserialization/deserialization (SerDes) circuitry to convert paralleldata to serial data for communication with the physical memory resourcesin the memory expander sled. In some instances, the memory controllersmay be integrated memory controllers with the processor or part of adifferent chipset of the sled with the physical compute resources.Further, the memory expander sled may also include SerDes circuitry toconvert the serial data to parallel data for communication with thememory modules.

In a fourth example, the physical memory resources of a memory expandersled may be shared between a number of physical compute resources andmay be in a single or individual sleds. The memory expander sled thephysical compute resources sled(s) may be coupled via a high speedserial link and each may include circuitry to convert data betweenparallel data and serial data. Further, the memory expander sled mayinclude a circuit switch to enable the sharing of the physical memoryresources with the physical compute resources. These and other detailswill become more apparent in the following description.

Reference is now made to the drawings, wherein like reference numeralsare used to refer to like elements throughout. In the followingdescription, for purposes of explanation, numerous specific details areset forth in order to provide a thorough understanding thereof. It maybe evident, however, that the novel embodiments can be practiced withoutthese specific details. In other instances, well-known structures anddevices are shown in block diagram form in order to facilitate adescription thereof. The intention is to cover all modifications,equivalents, and alternatives consistent with the claimed subjectmatter.

FIG. 1 illustrates a conceptual overview of a data center 100 that maygenerally be representative of a data center or other type of computingnetwork in/for which one or more techniques described herein may beimplemented according to various embodiments. As shown in FIG. 1, datacenter 100 may generally contain a plurality of racks, each of which mayhouse computing equipment comprising a respective set of physicalresources. In the particular non-limiting example depicted in FIG. 1,data center 100 contains four racks 102A to 102D, which house computingequipment comprising respective sets of physical resources (PCRs) 105Ato 105D. According to this example, a collective set of physicalresources 106 of data center 100 includes the various sets of physicalresources 105A to 105D that are distributed among racks 102A to 102D.Physical resources 106 may include resources of multiple types, suchas—for example—processors, co-processors, accelerators,field-programmable gate arrays (FPGAs), memory, and storage. Theembodiments are not limited to these examples.

The illustrative data center 100 differs from typical data centers inmany ways. For example, in the illustrative embodiment, the circuitboards (“sleds”) on which components such as CPUs, memory, and othercomponents are placed are designed for increased thermal performance. Inparticular, in the illustrative embodiment, the sleds are shallower thantypical printed circuit boards (PCBs). In other words, the sleds areshorter from the front to the back, where cooling fans are located. Thisdecreases the length of the path that air must to travel across thecomponents on the PCB. Further, the components on the sled are spacedfurther apart than in typical PCBs, and the components are arranged toreduce or eliminate shadowing (i.e., one component in the air flow pathof another component). In the illustrative embodiment, processingcomponents such as the processors are located on a top side of a sledwhile memory modules are located on a bottom side of the sled. As aresult of the enhanced airflow provided by this design, the componentsmay operate at higher frequencies and power levels than in typicalsystems, thereby increasing performance. Furthermore, the sleds areconfigured to blindly mate with power and data communication cables ineach rack 102A, 102B, 102C, 102D, enhancing their ability to be quicklyremoved, upgraded, reinstalled, and/or replaced. Similarly, individualcomponents located on the sleds, such as processors, accelerators,memory, and data storage drives, are configured to be easily upgradeddue to their increased spacing from each other. In the illustrativeembodiment, the components additionally include hardware attestationfeatures to prove their authenticity.

Furthermore, in the illustrative embodiment, the data center 100utilizes a single network architecture (“fabric”) that supports multipleother network architectures which may be in accordance to standards,such as Institute of Electrical and Electronics Engineers (IEEE)802.3-2015 standard (Ethernet) or any predecessors, revisions, orvariants thereof, and other architectures, such as Intel® Omni-Path®.The sleds, in the illustrative embodiment, are coupled to switches viaoptical fibers, which provide higher bandwidth and lower latency thantypical twisted pair cabling (e.g., Category 5, Category 5e, Category 6,etc.). Due to the high bandwidth, low latency interconnections andnetwork architecture, the data center 100 may, in use, pool resources,such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs,etc.), and data storage drives that are physically disaggregated, andprovide them to compute resources (e.g., processors) on an as neededbasis, enabling the compute resources to access the pooled resources asif they were local. The illustrative data center 100 additionallyreceives usage information for the various resources, predicts resourceusage for different types of workloads based on past resource usage, anddynamically reallocates the resources based on this information.

The racks 102A, 102B, 102C, 102D of the data center 100 may includephysical design features that facilitate the automation of a variety oftypes of maintenance tasks. For example, data center 100 may beimplemented using racks that are designed to be robotically-accessed,and to accept and house robotically-manipulable resource sleds.Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C,102D include integrated power sources that receive a greater voltagethan is typical for power sources. The increased voltage enables thepower sources to provide additional power to the components on eachsled, enabling the components to operate at higher than typicalfrequencies. FIG. 2 illustrates an exemplary logical configuration of arack 202 of the data center 100. As shown in FIG. 2, rack 202 maygenerally house a plurality of sleds, each of which may comprise arespective set of physical resources. In the particular non-limitingexample depicted in FIG. 2, rack 202 houses sleds 204-1 to 204-4comprising respective sets of physical resources 205-1 to 205-4, each ofwhich constitutes a portion of the collective set of physical resources206 comprised in rack 202. With respect to FIG. 1, if rack 202 isrepresentative of—for example—rack 102A, then physical resources 206 maycorrespond to the physical resources 105A comprised in rack 102A. In thecontext of this example, physical resources 105A may thus be made up ofthe respective sets of physical resources, including physical storageresources 205-1, physical accelerator resources 205-2, physical memoryresources 204-3, and physical compute resources 205-5 comprised in thesleds 204-1 to 204-4 of rack 202. The embodiments are not limited tothis example. Each sled may contain a pool of each of the various typesof physical resources (e.g., compute, memory, accelerator, storage). Byhaving robotically accessible and robotically manipulable sledscomprising disaggregated resources, each type of resource can beupgraded independently of each other and at their own optimized refreshrate.

FIG. 3 illustrates an example of a data center 300 that may generally berepresentative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. In theparticular non-limiting example depicted in FIG. 3, data center 300comprises racks 302-1 to 302-32. In various embodiments, the racks ofdata center 300 may be arranged in such fashion as to define and/oraccommodate various access pathways. For example, as shown in FIG. 3,the racks of data center 300 may be arranged in such fashion as todefine and/or accommodate access pathways 311A, 311B, 311C, and 311D. Insome embodiments, the presence of such access pathways may generallyenable automated maintenance equipment, such as robotic maintenanceequipment, to physically access the computing equipment housed in thevarious racks of data center 300 and perform automated maintenance tasks(e.g., replace a failed sled, upgrade a sled). In various embodiments,the dimensions of access pathways 311A, 311B, 311C, and 311D, thedimensions of racks 302-1 to 302-32, and/or one or more other aspects ofthe physical layout of data center 300 may be selected to facilitatesuch automated operations. The embodiments are not limited in thiscontext.

FIG. 4 illustrates an example of a data center 400 that may generally berepresentative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. As shown inFIG. 4, data center 400 may feature an optical fabric 412. Opticalfabric 412 may generally comprise a combination of optical signalingmedia (such as optical cabling) and optical switching infrastructure viawhich any particular sled in data center 400 can send signals to (andreceive signals from) each of the other sleds in data center 400. Thesignaling connectivity that optical fabric 412 provides to any givensled may include connectivity both to other sleds in a same rack andsleds in other racks. In the particular non-limiting example depicted inFIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example,data center 400 comprises a total of eight sleds. Via optical fabric412, each such sled may possess signaling connectivity with each of theseven other sleds in data center 400. For example, via optical fabric412, sled 404A-1 in rack 402A may possess signaling connectivity withsled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2,404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the otherracks 402B, 402C, and 402D of data center 400. The embodiments are notlimited to this example.

FIG. 5 illustrates an overview of a connectivity scheme 500 that maygenerally be representative of link-layer connectivity that may beestablished in some embodiments among the various sleds of a datacenter, such as any of example data centers 100, 300, and 400 of FIGS.1, 3, and 4. Connectivity scheme 500 may be implemented using an opticalfabric that features a dual-mode optical switching infrastructure 514.Dual-mode optical switching infrastructure 514 may generally comprise aswitching infrastructure that is capable of receiving communicationsaccording to multiple link-layer protocols via a same unified set ofoptical signaling media, and properly switching such communications. Invarious embodiments, dual-mode optical switching infrastructure 514 maybe implemented using one or more dual-mode optical switches 515. Invarious embodiments, dual-mode optical switches 515 may generallycomprise high-radix switches. In some embodiments, dual-mode opticalswitches 515 may comprise multi-ply switches, such as four-ply switches.In various embodiments, dual-mode optical switches 515 may featureintegrated silicon photonics that enable them to switch communicationswith significantly reduced latency in comparison to conventionalswitching devices. In some embodiments, dual-mode optical switches 515may constitute leaf switches 530 in a leaf-spine architectureadditionally including one or more dual-mode optical spine switches 520.Spine switches may include switches that can handle Layer 3 (L3) withhigh port density, which allows for scalability. In some instances, aspine switch is directly connected to a network control system with avirtual Layer 2 switch on top of the leaf-spine system.

In various embodiments, dual-mode optical switches may be capable ofreceiving both Ethernet protocol communications carrying InternetProtocol (IP packets) and communications according to a second,high-performance computing (HPC) link-layer protocol (e.g., Intel®Omni-Path Architecture®, Infiniband®) via optical signaling media of anoptical fabric. As reflected in FIG. 5, with respect to any particularrepair of sleds 504A and 504B possessing optical signaling connectivityto the optical fabric, connectivity scheme 500 may thus provide supportfor link-layer connectivity via both Ethernet links and HPC links. Thus,both Ethernet and HPC communications can be supported by a singlehigh-bandwidth, low-latency switch fabric. The embodiments are notlimited to this example.

FIG. 6 illustrates a general overview of a rack architecture 600 thatmay be representative of an architecture of any particular one of theracks depicted in FIGS. 1 to 4 according to some embodiments. Asreflected in FIG. 6, rack architecture 600 may generally feature aplurality of sled spaces into which sleds may be inserted, each of whichmay be robotically-accessible via a rack access region 601. In theparticular non-limiting example depicted in FIG. 6, rack architecture600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5feature respective multi-purpose connector modules (MPCMs) 616-1 to616-5. In some instances, when a sled is inserted into any given one ofsled spaces 603-1 to 603-5, the corresponding MPCM may couple with acounterpart MPCM of the inserted sled. This coupling may provide theinserted sled with connectivity to both signaling infrastructure andpower infrastructure of the rack in which it is housed.

Included among the types of sleds to be accommodated by rackarchitecture 600 may be one or more types of sleds that featureexpansion capabilities. FIG. 7 illustrates an example of a sled 704 thatmay be representative of a sled of such a type. As shown in FIG. 7, sled704 may comprise a set of physical resources 705, as well as an MPCM 716designed to couple with a counterpart MPCM when sled 704 is insertedinto a sled space such as any of sled spaces 603-1 to 603-5 of FIG. 6.Sled 704 may also feature an expansion connector 717. Expansionconnector 717 may generally comprise a socket, slot, or other type ofconnection element that is capable of accepting one or more types ofexpansion modules, such as an expansion sled 718. By coupling with acounterpart connector on expansion sled 718, expansion connector 717 mayprovide physical resources 705 with access to supplemental computingresources 705B residing on expansion sled 718. The embodiments are notlimited in this context.

FIG. 8 illustrates an example of a rack architecture 800 that may berepresentative of a rack architecture that may be implemented in orderto provide support for sleds featuring expansion capabilities, such assled 704 of FIG. 7. In the particular non-limiting example depicted inFIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7,which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to803-7 include respective primary regions 803-1A to 803-7A and respectiveexpansion regions 803-1B to 803-7B. With respect to each such sledspace, when the corresponding MPCM is coupled with a counterpart MPCM ofan inserted sled, the primary region may generally constitute a regionof the sled space that physically accommodates the inserted sled. Theexpansion region may generally constitute a region of the sled spacethat can physically accommodate an expansion module, such as expansionsled 718 of FIG. 7, in the event that the inserted sled is configuredwith such a module.

FIG. 9 illustrates an example of a rack 902 that may be representativeof a rack implemented according to rack architecture 800 of FIG. 8according to some embodiments. In the particular non-limiting exampledepicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7,which include respective primary regions 903-1A to 903-7A and respectiveexpansion regions 903-1B to 903-7B. In various embodiments, temperaturecontrol in rack 902 may be implemented using an air cooling system. Forexample, as reflected in FIG. 9, rack 902 may feature a plurality offans 919 that are generally arranged to provide air cooling within thevarious sled spaces 903-1 to 903-7. In some embodiments, the height ofthe sled space is greater than the conventional “1U” server height. Insuch embodiments, fans 919 may generally comprise relatively slow, largediameter cooling fans as compared to fans used in conventional rackconfigurations. Running larger diameter cooling fans at lower speeds mayincrease fan lifetime relative to smaller diameter cooling fans runningat higher speeds while still providing the same amount of cooling. Thesleds are physically shallower than conventional rack dimensions.Further, components are arranged on each sled to reduce thermalshadowing (i.e., not arranged serially in the direction of air flow). Asa result, the wider, shallower sleds allow for an increase in deviceperformance because the devices can be operated at a higher thermalenvelope (e.g., 250 W) due to improved cooling (i.e., no thermalshadowing, more space between devices, more room for larger heat sinks,etc.).

MPCMs 916-1 to 916-7 may be configured to provide inserted sleds withaccess to power sourced by respective power modules 920-1 to 920-7, eachof which may draw power from an external power source 921. In variousembodiments, external power source 921 may deliver alternating current(AC) power to rack 902, and power modules 920-1 to 920-7 may beconfigured to convert such AC power to direct current (DC) power to besourced to inserted sleds. In some embodiments, for example, powermodules 920-1 to 920-7 may be configured to convert 277-volt AC powerinto 12-volt DC power for provision to inserted sleds via respectiveMPCMs 916-1 to 916-7. The embodiments are not limited to this example.

MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds withoptical signaling connectivity to a dual-mode optical switchinginfrastructure 914, which may be the same as—or similar to—dual-modeoptical switching infrastructure 514 of FIG. 5. In various embodiments,optical connectors contained in MPCMs 916-1 to 916-7 may be designed tocouple with counterpart optical connectors contained in MPCMs ofinserted sleds to provide such sleds with optical signaling connectivityto dual-mode optical switching infrastructure 914 via respective lengthsof optical cabling 922-1 to 922-7. In some embodiments, each such lengthof optical cabling may extend from its corresponding MPCM to an opticalinterconnect loom 923 that is external to the sled spaces of rack 902.In various embodiments, optical interconnect loom 923 may be arranged topass through a support post or other type of load-bearing element ofrack 902. The embodiments are not limited in this context. Becauseinserted sleds connect to an optical switching infrastructure via MPCMs,the resources typically spent in manually configuring the rack cablingto accommodate a newly inserted sled can be saved.

FIG. 10 illustrates an example of a sled 1004 that may be representativeof a sled designed for use in conjunction with rack 902 of FIG. 9according to some embodiments. Sled 1004 may feature an MPCM 1016 thatcomprises an optical connector 1016A and a power connector 1016B, andthat is designed to couple with a counterpart MPCM of a sled space inconjunction with insertion of MPCM 1016 into that sled space. CouplingMPCM 1016 with such a counterpart MPCM may cause power connector 1016 tocouple with a power connector comprised in the counterpart MPCM. Thismay generally enable physical resources 1005 of sled 1004 to sourcepower from an external source, via power connector 1016 and powertransmission media 1024 that conductively couples power connector 1016to physical resources 1005.

Sled 1004 may also include dual-mode optical network interface circuitry1026. Dual-mode optical network interface circuitry 1026 may generallycomprise circuitry that is capable of communicating over opticalsignaling media according to each of multiple link-layer protocolssupported by dual-mode optical switching infrastructure 914 of FIG. 9.In some embodiments, dual-mode optical network interface circuitry 1026may be capable both of Ethernet protocol communications and ofcommunications according to a second, high-performance protocol. Invarious embodiments, dual-mode optical network interface circuitry 1026may include one or more optical transceiver modules 1027, each of whichmay be capable of transmitting and receiving optical signals over eachof one or more optical channels. The embodiments are not limited in thiscontext.

Coupling MPCM 1016 with a counterpart MPCM of a sled space in a givenrack may cause optical connector 1016A to couple with an opticalconnector comprised in the counterpart MPCM. This may generallyestablish optical connectivity between optical cabling of the sled anddual-mode optical network interface circuitry 1026, via each of a set ofoptical channels 1025. Dual-mode optical network interface circuitry1026 may communicate with the physical resources 1005 of sled 1004 viaelectrical signaling media 1028. In addition to the dimensions of thesleds and arrangement of components on the sleds to provide improvedcooling and enable operation at a relatively higher thermal envelope(e.g., 250 W), as described above with reference to FIG. 9, in someembodiments, a sled may include one or more additional features tofacilitate air cooling, such as a heatpipe and/or heat sinks arranged todissipate heat generated by physical resources 1005. It is worthy ofnote that although the example sled 1004 depicted in FIG. 10 does notfeature an expansion connector, any given sled that features the designelements of sled 1004 may also feature an expansion connector accordingto some embodiments. The embodiments are not limited in this context.

FIG. 11 illustrates an example of a data center 1100 that may generallybe representative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. As reflectedin FIG. 11, a physical infrastructure management framework 1150A may beimplemented to facilitate management of a physical infrastructure 1100Aof data center 1100. In various embodiments, one function of physicalinfrastructure management framework 1150A may be to manage automatedmaintenance functions within data center 1100, such as the use ofrobotic maintenance equipment to service computing equipment withinphysical infrastructure 1100A. In some embodiments, physicalinfrastructure 1100A may feature an advanced telemetry system thatperforms telemetry reporting that is sufficiently robust to supportremote automated management of physical infrastructure 1100A. In variousembodiments, telemetry information provided by such an advancedtelemetry system may support features such as failureprediction/prevention capabilities and capacity planning capabilities.In some embodiments, physical infrastructure management framework 1150Amay also be configured to manage authentication of physicalinfrastructure components using hardware attestation techniques. Forexample, robots may verify the authenticity of components beforeinstallation by analyzing information collected from a radio frequencyidentification (RFID) tag associated with each component to beinstalled. The embodiments are not limited in this context.

As shown in FIG. 11, the physical infrastructure 1100A of data center1100 may comprise an optical fabric 1112, which may include a dual-modeoptical switching infrastructure 1114. Optical fabric 1112 and dual-modeoptical switching infrastructure 1114 may be the same as—or similarto—optical fabric 412 of FIG. 4 and dual-mode optical switchinginfrastructure 514 of FIG. 5, respectively, and may providehigh-bandwidth, low-latency, multi-protocol connectivity among sleds ofdata center 1100. As discussed above, with reference to FIG. 1, invarious embodiments, the availability of such connectivity may make itfeasible to disaggregate and dynamically pool resources such asaccelerators, memory, and storage. In some embodiments, for example, oneor more pooled accelerator sleds 1130 may be included among the physicalinfrastructure 1100A of data center 1100, each of which may comprise apool of accelerator resources—such as co-processors and/orfield-programmable gate arrays (FPGAs), for example—that is availableglobally accessible to other sleds via optical fabric 1112 and dual-modeoptical switching infrastructure 1114.

In another example, in various embodiments, one or more pooled storagesleds 1132 may be included among the physical infrastructure 1100A ofdata center 1100, each of which may comprise a pool of storage resourcesthat is available globally accessible to other sleds via optical fabric1112 and dual-mode optical switching infrastructure 1114. In someembodiments, such pooled storage sleds 1132 may comprise pools ofstorage devices such as solid-state drives (SSDs), hard disk drives(HDD), hard drive, disk drive, fixed disk drives, and so forth. Invarious embodiments, one or more high-performance processing sleds 1134may be included among the physical infrastructure 1100A of data center1100. In some embodiments, high-performance processing sleds 1134 maycomprise pools of high-performance processors, as well as coolingfeatures that enhance air cooling to yield a higher thermal envelope ofup to 250 Watts (W) or more. In various embodiments, any givenhigh-performance processing sled 1134 may feature an expansion connector1117 that can accept a memory expansion sled, such that the next level(second level or third level) memory that is locally available to thathigh-performance processing sled 1134 is disaggregated from theprocessors and memory comprised on that sled. In some embodiments, sucha high-performance processing sled 1134 may be configured with the nextlevel memory using an expansion sled that comprises low-latency SSD. Theoptical infrastructure allows for compute resources on one sled toutilize remote accelerator/FPGA, memory, and/or storage resources thatare disaggregated on a sled located on the same rack or any other rackin the data center. The remote resources can be located one switch jumpaway or two-switch jumps away, e.g. remote resources connected through asingle or two switches, in the spine-leaf network architecture describedabove with reference to FIG. 5. The embodiments are not limited in thiscontext.

In various embodiments, one or more layers of abstraction may be appliedto the physical resources of physical infrastructure 1100A in order todefine a virtual infrastructure, such as a software-definedinfrastructure 1100B. In some embodiments, virtual computing resources1136 of software-defined infrastructure 1100B may be allocated tosupport the provision of cloud services 1140. In various embodiments,particular sets of virtual computing resources 1136 may be grouped forprovision to cloud services 1140 in the form of software definedinfrastructure (SDI) services 1138. Examples of cloud services 1140 mayinclude—without limitation—software as a service (SaaS) services 1142,platform as a service (PaaS) services 1144, and infrastructure as aservice (IaaS) services 1146.

In some embodiments, management of software-defined infrastructure 1100Bmay be conducted using a virtual infrastructure management framework1150B. In various embodiments, virtual infrastructure managementframework 1150B may be designed to implement workload fingerprintingtechniques and machine-learning techniques in conjunction with managingallocation of virtual computing resources 1136 and/or SDI services 1138to cloud services 1140. In some embodiments, virtual infrastructuremanagement framework 1150B may use/consult telemetry data in conjunctionwith performing such resource allocation. In various embodiments, anapplication/service management framework 1150C may be implemented toprovide quality of service (QoS) management capabilities for cloudservices 1140. The embodiments are not limited in this context.

FIG. 12 illustrates an example of a compute system 1200 that includes asled 1204 coupled with physical memory resources 1205-3, which may beincorporated in a memory expander sled 1218. In embodiments, the sled1204 includes a connector 1217 to couple with a connector 1219 of thememory expander sled 1218. The sled 1204 is capable of communicatingdata via a high speed serial link 1251 with the memory expander sled1218 and the physical memory resources 1205-3. The memory expander sled1218 and physical memory resources 1205-3 may be utilized to store andaccess data for the physical compute resources 1205-4 of the sled 1204,for example. Having a memory expander sled 1218 with physical memoryresources 1205-3 coupled with the physical compute resources 1205-4 mayalso enable disaggregation of the physical compute resources 1205-4 fromthe physical memory resources 1205-3. Thus, the physical computeresources 1205-4 or the physical memory resources 1205-3 may be replacedwithout affecting the remaining physical resource (memory or compute) inthe compute system 1200.

In embodiments, the sled 1204 may be the same as other sleds discussedherein, such as sled 1004 illustrated in FIG. 10, and include similarcomponents. For example, the sled 1204 includes physical computeresources 1205-4, which may further include one or more cores 1207-1through 1207-a, where a may be any positive integer. The physicalcompute resource 1205-4 also includes a memory controller 1236 and amemory interface 1234 that may couple with the connector 1217 via a highspeed serial link 1251, which may be an electrical or opticalinterconnect or bus and capable of communicating data in serial.

In embodiments, the physical compute resource 1205-4 may be implementedas a microprocessor, a processor, a central processing unit, amulti-core processor, a mobile device processor, a single coreprocessor, a system-on-chip (SoC) device, and so forth. The physicalcompute resource 1205-4 may be integrated on a single die or multipledies in a single chip package. Moreover, each of the cores 1207 of thephysical compute resources 1205-4 may be independent processing unitscapable of reading and executing program instructions. The instructionsare ordinary instructions that can be executed at the same time or inparallel. In embodiments, the physical compute resource 1205-4 may becoupled with other components of the sled 1204 via one or moreinterconnects or links.

The physical compute resource 1205-4 also includes a memory controller1236, which may be an integrated memory controller on the same die asthe cores 1207. In other instances, the memory controller 1236 may beintegrated into a different die on a different chipset and couple withthe cores 1207 by a bus or link, for example. The memory controller 1236may receive read requests and memory address(es) to read data frommemory, e.g. the physical memory resources 1205-3. Data may be read fromthe physical memory resources 1205-3 of the memory expander sled 1218.The memory controller 1236 may provide the data to the cores 1207 onceit is read from memory, for example. Further, the memory controller 1236may also receive write requests, memory address(es) and associated datato write to the physical memory resources 1205-3 of the memory expandersled 1218.

In some embodiments, the physical memory resources 1205-3 including thememory modules 1211 may include one or more byte addressablewrite-in-place non-volatile memory devices. The memory devices may alsoinclude future generation non-volatile devices, such as a threedimensional crosspoint memory device, or other byte addressablewrite-in-place nonvolatile memory devices. In one embodiment, the memorydevices may be or may include memory devices that use chalcogenideglass, multi-threshold level NAND flash memory, NOR flash memory, singleor multi-level Phase Change Memory (PCM), a resistive memory, nanowirememory, ferroelectric transistor random access memory (FeTRAM),anti-ferroelectric memory, magnetoresistive random access memory (MRAM)memory that incorporates memristor technology, resistive memoryincluding the metal oxide base, the oxygen vacancy base and theconductive bridge Random Access Memory (CB-RAM), or spin transfer torque(STT)-MRAM, a spintronic magnetic junction memory based device, amagnetic tunneling junction (MTJ) based device, a DW (Domain Wall) andSOT (Spin Orbit Transfer) based device, a thiristor based memory device,or a combination of any of the above, or other memory. The memorydevices may refer to the die itself and/or to a packaged memory product.In some embodiments, the memory modules 1211 may include other types ofmemory devices, such as dynamic RAM (DRAM), static RAM (SRAM), doubledata rate DRAM (DDR DRAM), synchronous DRAM (SDRAM), DDR SDRAM, and soforth. Some embodiments may include a combination of different memorytypes, embodiments are not limited in this manner.

In some embodiments, the memory module 1211 may be a dual in-line memorymodule (DIMM) having one or more memory devices capable of plugging intoa DIMM slot of a PCB of the memory expander sled 1218. The module 1211may have a DIMM form factor in accordance with one or more standards,such as Joint Electronic Device Engineering Council (JEDEC) definedtechnical standard JESD248 (“DDR NVDIMM-N Design Standard”), JEDECModule 4.20.27 (“288-Pin, 1.2 V (VDD),PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM LoadReduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”),JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD),PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAMRegistered DIMM Design Specification”), and so forth. Embodiments arenot limited in this manner. In some instances, the memory module 1211may be integrated circuit memory devices incorporated directly on a PCBof the memory expander sled 1218.

In embodiments, the memory controller 1236 may be coupled with a memoryinterface 1234 via a parallel link 1253, wherein the memory interface1234 is capable of interfacing with the physical memory resources 1205-3of the memory expander sled 1218 via a high speed serial link 1251. Theparallel link 1253 may be a high-speed parallel link or bus tocommunicate data in parallel and coupled with the memory interface 1234and the high speed serial link 1251 may be a link to communicate data inserial. The memory interface 1234 may also include circuitry tocommunicate data between the memory controller 1234 and the memorymodule(s) 1211. For example, the memory interface 1234 may include anoptical transceiver to communicate data via an optical high speed seriallink. In another example, the memory interface 1234 may include anelectrical transceiver to communicate via electrical high speed seriallinks.

The memory interface 1234 may also include circuitry, such asserializer/deserializer (SerDes) circuitry, to convert parallel data toserial data, and vice versa. More specifically, the memory interface1234 can convert parallel data communicated from one or more cores 1207to serial data for communication to the memory module(s) 1211 via thehigh speed serial links 1251. Similarly, the memory interface 1234 mayconvert serial data received from the memory module(s) 1211 to paralleldata for communication to the one or more cores 1207 via the high speedparallel links 1253. Embodiments are not limited to this example, and insome instances, the SerDes circuitry may be incorporated into theconnector 1217 instead of the memory interface 1234.

In some embodiments, the memory interface 1234 may include circuitry tocompress and decompress data communicated via the high speed serial link1251. For example, a compression mechanism may be used to generate afabric packet including the compressed data to communicate serial viathe high speed serial links 1251. The compression mechanism may utilizea compression algorithm, such as a Byte Pattern Repeat compressionmechanism, a Word (2 bytes) Pattern Repeat compression mechanism, aDword (4 bytes) Pattern Repeat compression mechanism, and a Qword (8bytes) Pattern Repeat. In some instances, other compression mechanismsmay be utilized, such as compression logic or an algorithm to performlossless data compression on the data. In one example, a run-lengthencoding (RLE) algorithm may be used on the data such that a repeatingpattern and the length of the repeating pattern are indicated in thecompressed data. Other examples of compression algorithms that may beused include Lempel-Ziv 1978, Lempel-Ziv Fast (LZF), DEFLATE, bzip2,Lempel-Ziv-Markov chain algorithm, Lempel-Ziv-Oberhumer, and so forth.

In some embodiments, the memory interface 1234 may communicateinformation and data including packets using a transaction protocol. Thetransaction protocol may enable transaction-based data transfers usingthe high speed interconnect 1251. For example, the high speedinterconnect may support a Quick-Path Interconnect transaction protocolthat may employ packet-based transfers using a multi-layer protocolarchitecture. Among its features is support for coherent transactions(e.g., memory coherency). In embodiments, to increase memory transactionbandwidth, a Fully Buffered DIMM (or FB-DIMM) architecture is employed,which introduces an advanced memory buffer (AMB) between the memorycontroller 1236 and a memory module 1211. Unlike the parallel busarchitecture of traditional DRAMs, the high speed serial link 1251enables an increase in the width of the memory without increasing thepin count of the memory controller 1236 beyond a feasible level. Inanother example, the high speed serial link 1251 may be a scalablememory interconnect (SMI) link and include Scalable Memory Buffers(SMB).

The memory interface 1234 may be coupled to the connector 1217 via ahigh speed serial link 1251. In some embodiments, the connector 1217 maybe a low pin count high-speed slot connector capable of receiving andcoupling with the connector 1219 of the memory expander sled 1218. Inone example, the connector 1217 may be a serial attachment (SATA)connector, a micro SATA (mSATA) connector, a SATA2 connector a SATA3connector, a SATA4 connector, a universal serial bus (USB) connector, aUSB3 connector, a SATAe connector, a Thunderbolt 3 connector, aconnector in accordance with JEDEC defined technical standard, such asthe MO-297 standard, and the MO-300 standard. Other examples, mayinclude a Next Generation Form Factor (NGFF) connector or an M.2connector. In some embodiments, the connector 1217 may provide anoptical connection, e.g. an optical fiber connector. Embodiments are notlimited to these examples and other high speed serial connectors may beutilized for the connectors 1217 and 1219.

In some instances, the form factor of the memory expander sled 1218 maydetermine which connector type is utilized for connectors 1217 and 1219.For example, the memory expander sled 1218 may be in a solid state drive(SSD) form factor and the memory module(s) 1211 may include one or morebyte addressable write-in-place non-volatile memory devices, or anyother memory device, as previously discussed. In some instances, thememory expander sled 1218 may not incorporate memory modules, but mayhave integrated circuit memory devices incorporated directly on aprinted circuit board (PCB) of the memory expander sled 1218.Embodiments are not limited in this manner.

The SSD form factor may be in accordance with the JEDEC MO-297-A (May2009) standard or any predecessors, revisions, or variants thereof.Other examples include SSD form factors in accordance with a NextGeneration Form Factor (NGFF) or an M.2 form factor. The connectors 1217and 1219 may be one of the SATA connectors, e.g. SATA2, SATA3, SATA4,etc., or other high speed serial connectors for connecting with a SSDform factor. In this example, the SSD form factor enables the sled 1204having the physical compute resource 1205-4 to be changed withoutchanging the memory expander sled 1218 and memory modules 1211 orallowing them to be reused with other physical compute resources 1205-4.

In another example, the memory expander sled 1218 may have a DIMM formfactor and the memory module 1211 may be integrated circuit memorydevices incorporated on the PCB of the memory expander sled 1218. Theconnector 1217 of the sled 1204 may be a pig tail type connector capableof coupling with connector 1219 of the memory expander sled 1218 via ahigh speed serial link 1251. The DIMM form factor of the memory expandersled 1218 may be in accordance with one or more standards, such as JEDECdefined technical standard JESD248 (“DDR NVDIMM-N Design Standard”),JEDEC Module 4.20.27 (“288-Pin, 1.2 V (VDD),PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM LoadReduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”),JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD),PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAMRegistered DIMM Design Specification”), and so forth. Embodiments arenot limited in this manner. In this example, the connector 1217,configured as a pig tail, may be added as DIMM connector to the PCB ofthe sled 1204. The connector 1217 may couple with a high speed seriallink, which may be low pin count cable or wire that is part of the pigtail having an opposing end that may couple with a DIMM connector(connector 1219) of the memory expander sled 1218. In this example, theconnectors 1217 and 1219 may include SerDes circuitry to convert datafrom parallel to serial, and vice versa, for communication via the lowpin count wire between the memory expander sled 1218 and the sled 1204.Note that FIG. 12 only includes a single sled 1204 coupled with a singlememory expander sled 1218. However, embodiments are not limited inmanner. In some instances, the sled 1204 may include a number ofconnectors 1217, each configured as a pig tail and coupled with acorresponding memory expander sled 1218, for example.

On the memory expander sled 1218, the connector 1219 may be coupled witha physical memory resource 1205-3, including a memory interface 1209 viaa high speed serial link 1251 or a high speed parallel link (not shown)for instances when the SerDes circuitry is incorporated in the connector1219 itself. Data may be passed or communicated to the memory interface1209, which may include at least one of an optical transceiver andelectrical transceiver to communicate data between the memory module(s)1211 and the memory controller 1236 of the sled 1204. In some instances,the memory interface 1209 may also include SerDes circuitry to convertparallel data to serial data. Thus, data communicated from the connector1219 to the memory interface 1209 in a serial data format and the memoryinterface 1209 may convert the data back to parallel data for the memorymodule(s) 1211. Similarly, parallel data communicated from the memorymodule(s) 1211 may be serialized by the memory interface 1209 forcommunication to the sled 1204. The memory interface 1209 may alsoinclude circuitry to perform compression and decompression andcommunicate data via a transactional protocol, as previously discussed.

In embodiments, the memory interface 1209 may receive the read requestsfrom memory interface 1234, which may include one or more address(es) toread data from the memory modules 1211. The data may be read from thememory modules 1211 and the memory interface 1209 may provide the dataover the high speed serial link 1251, as discussed. Similarly, thememory interface 1209 may also receive write requests from memoryinterface 1234, which may include one or more address(es) and data thatmay be written into memory modules 1211. The data may be written intothe memory modules 1211 based on the one or more address(es).

FIG. 13 illustrates an example of a compute system 1300 that maygenerally be representative of a sled 1304 coupled with an add-incomponent, such as a memory expander sled 1318 having physical memoryresources 1305-3. In embodiments, the compute system 1300 may be similarto compute system 1200 of FIG. 12. Further and in some embodiments, sled1304 may be the same as other sleds discussed herein, such as sled 1004illustrated in FIG. 10 and sled 1204 of FIG. 12, and include similarcomponents. For example, the sled 1304 includes physical computeresources 1305-4, which may further include one or more cores 1307-1through 1307-a, where a may be any positive integer. The physicalcompute resource 1305-4 also includes a number of memory controllers1336-1 through 1336-4 and a number of memory interfaces 1334-1 through1334-4 that may couple with a connector 1317 via a high speed seriallink 1351. The illustrated example of FIG. 13 only shows four memorycontrollers 1336-1 through 1336-4 and four memory interfaces 1334-1through 1334-4. However, embodiments are not limited in this manner andembodiments may include more or fewer memory controllers 1336 and memoryinterfaces 1334.

In embodiments, the physical compute resource 1305-4 may be implementedvia a processor, computer processing unit, multi-core processor, and soforth as similarly discussed with respect physical compute resources1205-4 of FIG. 12. The physical compute resource 1305-4 may beintegrated on a single die or multiple dies in a single chip package,for example. In FIG. 13 the physical compute resource 1305-4 includesfour memory controllers 1336-1 through 1336-4, each of which may be anintegrated memory controller on the same die as the cores 1307. In otherinstances, the memory controllers 1336-1 through 1336-4 may beintegrated into a different die on a different chipset and couple withthe cores 1307 by a bus, for example.

Each of the memory controllers 1336-1 through 1336-4 may process readand write requests. Further, each of the memory controllers 1336-1through 1336-4 may provide a memory channel in a multi-channel memoryarchitecture. Each of the memory channels may enable communicationbetween the memory controllers 1336-1 through 1336-4 and one or more ofthe memory modules 1311-1 through 1311-8. In some instances, thethroughput may be 50 GigaTransfers/second (GT/s)/Channel. Theillustrated embodiment includes four channels; however, embodiments arenot limited in this manner and embodiments may include more or fewerchannels.

In embodiments, each of the memory controllers 1336-1 through 1336-4 maybe coupled with a corresponding memory interface 1334-1 through 1334-4via parallel links 1353. The parallel links 1353 may be high-speedparallel links or a bus coupled with the memory interfaces 1334-1through 1334-4. In embodiments, each of the memory interface 1334-1through 1334-4 may include circuitry, e.g. an optical and/or electricaltransceiver, to communicate data between the corresponding memorycontrollers 1336-1 through 1336-4 and the memory modules 1311-1 through1311-8. Each of the memory interfaces 1334-1 through 1334-4 may alsoinclude circuitry, such as SerDes circuitry, to convert parallel data toserial data, and vice versa. Thus, data communicated from one or morecores 1307 may be converted from parallel data to serial data forcommunication to the memory modules 1311-1 through 1311-8 by the memoryinterfaces 1334-1 through 1334-4. Similarly, the memory interfaces1334-1 through 1334-4 may convert serial data received from the memorymodules 1311-1 through 1311-8 to parallel data for communication to theone or more cores 1307. Embodiments are not limited in this manner andsome instances, the SerDes circuitry may be implemented as part of theconnector 1317. In this example, memory interfaces 1334 may be coupledwith the connector 1317 via parallel links and the connector 1317 mayconvert the data. However, if each of the memory interfaces 1334-1through 1334-4 includes SerDes circuitry, they may also circuitry tosend and receive data via at least one of optical serial links andelectrical serial links, perform compression and decompression of thedata, and use a transactional protocol.

In embodiments, the memory interfaces 1334-1 through 1334-4 may becoupled with a connector 1317 via a high speed serial link 1351 or aparallel link depending on whether the parallel to serial (or viceversa) conversation occurs in the memory interface 1334 or the connector1317. In embodiments, the connector 1317 may couple with connector 1319of the memory expander sled 1318 via the high speed serial links 1351.Each high speed serial link 1351 may provide a memory channel for themulti-channel memory architecture. In embodiments, the connectors 1317and 1319 may provide at least one of an optical high-speed serialconnection and electrical high-speed serial connection via the highspeed serial link 1351.

Moreover, the connector 1319 of the memory expander sled 1818 maycommunicate data with the sled 1304 via the high speed serial links1351, as discussed. In some instances, the connector 1319 also includesSerDes circuitry to convert data from parallel data to serial data tocommunicate to the memory modules 1311, and vice versa to communicatedata to the sled 1304. The connector 1319 may be coupled with thephysical memory resource 1305-3, and in particular, memory interfaces1309-1 through 1309-4. Although FIG. 13 illustrates four memoryinterfaces 1309-1 through 1309-4, embodiments are not limited in thismanner and may include more or fewer interfaces.

Each of the memory interfaces 1309-1 through 1309-4 may be coupled withthe connector 1319 via a parallel link if the connector 1319 includesthe SerDes circuitry or a high speed serial link 1351 if the memoryinterfaces 1309 include the SerDes circuitry. In embodiments, each ofthe memory interfaces 1309-1 through 1309-4 may also include circuitry,e.g. an electrical or optical transceiver, to send and receive data viaoptical serial links and electrical serial links. Each of the memoryinterfaces 1309-1 through 1309-4 may be capable of receiving and sendingdata between the memory module(s) 1311-1 through 1311-8 of the memoryexpander sled 1318 and the sled 1304. In instances, the data may becommunicated via high-speed parallel links 1353 with the memory modules1311-1 through 1311-8.

In embodiments, the physical memory resources 1305-3 may include anumber of memory modules 1311-1 through 1311-8, each of which includeone or more byte addressable write-in-place non-volatile memory devices.The memory devices may also include future generation non-volatiledevices, such as a three dimensional crosspoint memory device, or otherbyte addressable write-in-place nonvolatile memory devices. In oneembodiment, the memory devices may be or may include memory devices thatuse chalcogenide glass, multi-threshold level NAND flash memory, NORflash memory, single or multi-level Phase Change Memory (PCM), aresistive memory, nanowire memory, ferroelectric transistor randomaccess memory (FeTRAM), anti-ferroelectric memory, magnetoresistiverandom access memory (MRAM) memory that incorporates memristortechnology, resistive memory including the metal oxide base, the oxygenvacancy base and the conductive bridge Random Access Memory (CB-RAM), orspin transfer torque (STT)-MRAM, a spintronic magnetic junction memorybased device, a magnetic tunneling junction (MTJ) based device, a DW(Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristorbased memory device, or a combination of any of the above, or othermemory. The memory devices may refer to the die itself and/or to apackaged memory product. In some embodiments, the memory modules 1211may include other types of memory devices, such as dynamic RAM (DRAM),static RAM (SRAM), double data rate DRAM (DDR DRAM), synchronous DRAM(SDRAM), DDR SDRAM, and so forth. Some embodiments may include acombination of different memory types, embodiments are not limited inthis manner. In some embodiments, the memory module 1311 may be a dualin-line memory module (DIMM) having one or more memory devices capableof plugging into a DIMM slot of a PCB of the memory expander sled 1318.The memory module 1311 may have a DIMM form factor in accordance withone or more standards, such as Joint Electronic Device EngineeringCouncil (JEDEC) defined technical standard JESD248 (“DDR NVDIMM-N DesignStandard”), JEDEC Module 4.20.27 (“288-Pin, 1.2 V (VDD),PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM LoadReduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”),JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD),PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAMRegistered DIMM Design Specification”), and so forth. Embodiments arenot limited in this manner.

In embodiments, the memory expander sled 1318 coupled with the sled 1304via the connectors 1317 and 1319 and the high speed serial links 1351may enable disaggregation of the physical compute resources 1305-4 fromthe physical memory resources 1305-3. Thus, the physical computeresources 1305-4 or the physical memory resources 1305-3 may be replacedwithout affecting the remaining physical resource (memory or compute) inthe compute system 1300.

FIG. 14 illustrates an example of a compute system 1400 that maygenerally include a sled 1404 coupled with an add-in component, such asa memory expander sled 1418 having physical memory resources 1405-3. Insome instances, the sled 1404 may be a processor cartridge as part of arack-scale system. In embodiment compute system 1400 may be similar tocompute systems 1200 and 1300 of FIGS. 12 and 13. The sled 1404 mayinclude a number of physical compute resources 1405-4-1 through1405-4-x, where x may be any positive integer. Further and in someembodiments, the sled 1404 may be the same as other sleds discussedherein, such as sleds 1004, 1204, and 1304 illustrated in FIGS. 10, 12and 13, and include similar components. In some instances, each of thephysicals compute resources 1405-4 may be incorporated into their ownsled 1404. Embodiments are not limited in this manner.

In instances, each of the physical compute resources 1405-4 may includeone or more cores (not shown), one or more memory controllers 1436, andone or more memory interfaces 1434. These components may be similar orthe same as the liked named components as previously discussed in FIGS.12 and 13. For example, each of the physical resources 1405-4 mayinclude memory controllers 1436 to process read and write requests formemory, and communicate with memory interfaces 1434 via high-speedparallel links (not shown). Further, the memory interfaces 1434 mayinclude circuitry to communicate the data and convert the parallel datato serial data for communication via the high-speed serial links 1451.In some instances, the memory interfaces 1434 may include SerDescircuitry to convert parallel data to serial data and vice versa, forexample. The serial data may be communicated via the high-speed seriallinks 1451, which may be optical high-speed serial links or electricalhigh-speed serial links capable of communicating data at 50GigaTransfers/second (GT/s). In some instances, the high speed seriallinks 1451 may be capable of communicating data at 50 GT/s for eachmemory channel in a multi-channel memory architecture.

In embodiments, the memory interfaces 1434 may be coupled to a connector1417 via high speed serial links 1451. Although not shown, in someinstances the memory interfaces 1434 may be coupled to connector 1417via parallel links, and the connector 1417 may include SerDes circuitryto convert data between parallel and serial formats. Further, theconnector 1417 may couple with connector 1419 of the memory expandersled 1418 via high speed serial links 1451 to electrically and/oroptically link the two sleds 1404 and 1418 together. In some instances,each high speed serial link 1451 linking the two sleds 1404 and 1418 mayprovide a memory channel for a multi-channel memory architecture.Similar to connector 1417, the connector 1419 of the memory expandersled 1418 may also include SerDes circuitry to convert data fromparallel data to serial data and vice versa. However, embodiments arenot limited in this manner and some instances; memory interfaces 1409may include the SerDes circuitry to convert serial data to parallel dataand vice versa. The memory interfaces 1434 may also include circuitry toperform compression/decompression of the data and communicate via atransactional protocol.

The connector 1419 may be coupled with a circuit switch 1414, such as anelectrical circuit switch (flit or FED) or an optical circuit switch.The circuit switch 1414 may enable the physical compute resources 1405to share memory, such as the memory modules 1411 of physical memoryresource 1405-3. In some instances, the circuit switch 1414 may beincorporated in or be part of the connector 1419. The circuit switch1414 may couple one or more memory modules 1411 with a physical computeresource 1405-4 for utilization by the physical compute resources 1405-4to process data and workloads.

In some instances, the circuit switch 1414 may include circuitry todetermine workloads for the physical compute resource 1405-4 and arequired amount of memory to process those workloads. The circuit switch1414 may dynamically assign memory modules 1411 (and channels) for useby a physical compute resource 1405-4 during run-time to process aworkload, for example. Once a workload is complete or processed, thecircuit switch 1414 may configure or reallocate memory modules 1411 toprocess another workload. The reallocation and configuration of whichmemory modules 1411 are used by which physical compute resource 1405-4may occur continuously, and in real-time, while the compute system 1400is processing workloads.

The circuit switch 1414 may also be configurable based on informationreceived by a controller. For example, a baseboard management controller(not shown) of a sled 1404 may communicate information and control thecircuit switch 1414. The information may indicate a circuit switchconfiguration or information of workloads, which may be used by thecircuit switch 1414 to make the determination of configuration. Thecircuit switch 1414 may receive information from other controllers ofthe compute system 1400, such as pod management controller and a rackmanagement controller. In some instances, the circuit switch 1414 may beconfigured or reconfigured at a time of a boot or reboot. For example,if one or more of the physical compute resources 1405-4 are rebooted orbooted, the circuit switch 1414 may configure itself to allocate memorymodules 1411 accordingly, e.g. to process workloads based on arequirement of the physical compute resources 1405. Embodiments are notlimited in this manner.

The physical memory resource 1405-3 may include any number of memorymodules 1411-c, where c may be any positive integer. Moreover, thememory modules 1411 may be shared with the physical compute resources1405-4 via the circuit switch 1414; and therefore, may be considered apool of memory modules 1411. each of which include one or more byteaddressable write-in-place non-volatile memory devices. The memorydevices may also include future generation non-volatile devices, such asa three dimensional crosspoint memory device, or other byte addressablewrite-in-place nonvolatile memory devices. In one embodiment, the memorydevices may be or may include memory devices that use chalcogenideglass, multi-threshold level NAND flash memory, NOR flash memory, singleor multi-level Phase Change Memory (PCM), a resistive memory, nanowirememory, ferroelectric transistor random access memory (FeTRAM),anti-ferroelectric memory, magnetoresistive random access memory (MRAM)memory that incorporates memristor technology, resistive memoryincluding the metal oxide base, the oxygen vacancy base and theconductive bridge Random Access Memory (CB-RAM), or spin transfer torque(STT)-MRAM, a spintronic magnetic junction memory based device, amagnetic tunneling junction (MTJ) based device, a DW (Domain Wall) andSOT (Spin Orbit Transfer) based device, a thiristor based memory device,or a combination of any of the above, or other memory. The memorydevices may refer to the die itself and/or to a packaged memory product.In some embodiments, the memory modules 1211 may include other types ofmemory devices, such as dynamic RAM (DRAM), static RAM (SRAM), doubledata rate DRAM (DDR DRAM), synchronous DRAM (SDRAM), DDR SDRAM, and soforth. Some embodiments may include a combination of different memorytypes, embodiments are not limited in this manner.

In embodiments, the memory modules 1411 may be in memory expander sled1418 in an SSD form factor and may use any SATA connector, as previouslydiscussed. For example, The SSD form factor may be in accordance withthe JEDEC MO-297-A (May 2009) standard or any predecessors, revisions,or variants thereof. Other examples include SSD form factors inaccordance with a Next Generation Form Factor (NGFF) or an M.2 formfactor. The connectors 1417 and 1419 may be one of the SATA connectors,e.g. SATA2, SATA3, SATA4, etc., or other high speed serial connectorsfor connecting with a SSD form factor. Embodiments are not limited tothese examples, and other SSD form factors may be utilized and beconsistent with embodiments discussed herein.

In embodiments, the memory expander sled 1418 coupled with the sled 1404via the connectors 1417 and 1419 and the high speed serial links 1451may enable disaggregation of the physical compute resources 1405-4 fromthe physical memory resources 1405-3. Thus, the physical computeresources 1405-4 or the physical memory resources 1405-3 may be replacedwithout affecting the remaining physical resource (memory or compute) inthe compute system 1400.

FIG. 15 illustrates an embodiment of logic flow 1500 and logic flow1550. The logic flows 1500 and 1550 may be representative of some or allof the operations executed by one or more embodiments described herein.For example, the logic flows 1500 and 1550 may illustrate operationsperformed by a memory interface of a sled having physical computeresources, However, embodiments are not limited in this, and one or moreoperations may be performed by other components or systems discussedherein, such as a connector.

With respect to logic flow 1500, embodiments include receiving data viaa high speed parallel link from a core of physical compute resource atblock 1502. In some instances, the data may be data a core requests tostore or write to memory. The data may be communicated to a memoryinterface via a memory controller and may also be communicated withaddress information for use by the memory to store the data.

At block 1504, the logic flow 1500 may include converting the datareceived via the high speed parallel link for communication via a highspeed serial link. For example, the memory interface may serialize thedata, via SerDes circuitry, to communicate the data via asingle/differential link. In embodiments, the SerDes circuitry mayconvert the data for communication via a high speed serial link usingany number of techniques, including but not limited to, a parallel clockSerDes technique, an Embedded clock SerDes technique, a 8b/10b SerDestechnique, and a bit interleaved SerDes technique. To convert the datafor serial communication, the SerDes circuitry may receive a parallelclock input, a set of data input lines (parallel link), and input datalatches. The SerDes circuitry may utilize a phase-locked looped tomultiply the incoming parallel clock up to a serial frequency for thehigh speed serial link.

At block 1506, the logic flow 1500 may include sending the data via thehigh speed serial link to one or more memory modules. In some instances,the one or more memory modules may be incorporated on a memory expandersled to enable easy disaggregation of the memory modules and the cores.

With respect to logic flow 1550, embodiments include receiving data viaa high speed serial link from a memory of a memory expander sled atblock 1522. In some instances, the data may be data a core requests tobe read from the memory and may be received based on a read request. Thedata may be communicated to the memory interface via a memory interfaceof a memory expander sled. In some instances, data may be received froma circuit switch coupled with the memory interface of the memoryexpander sled.

At block 1554, the logic flow 1550 may include converting the datareceived via high speed serial link for communication via a high speedparallel link. For example, the memory interface may deserialize thedata, via SerDes circuitry, to communicate the data via a parallel link.In embodiments, the SerDes circuitry may convert the data forcommunication via a high speed parallel link using any number oftechniques, including but not limited to, the parallel clock SerDestechnique, the Embedded clock SerDes technique, the 8b/10b SerDestechnique, and the bit interleaved SerDes technique. To convert the datafor parallel, the SerDes circuitry may utilize a receive clock output toclock down to a parallel data rate for communication of the data via theparallel link. The data may be communicated via a set of output linesusing output data latches to the cores. based on the parallel rate, forexample. In some instances, a buffer (two registers) may be used toclock down the data from the high serial link to the parallel link rate.At block 1556, the logic flow 1500 may include sending the data via thehigh speed parallel link to a core.

FIG. 16 illustrates an embodiment of logic flow 1600 and logic flow1650. The logic flows 1600 and 1650 may be representative of some or allof the operations executed by one or more embodiments described herein.For example, the logic flows 1600 and 1650 may illustrate operationsperformed by a memory interface of a memory expander sled havingphysical memory resources, However, embodiments are not limited in this,and one or more operations may be performed by other components orsystems discussed herein, such as a connector.

With respect to logic flow 1600, embodiments include receiving data viaa high speed parallel link from a memory module of physical memoryresource at block 1602. In some instances, the data may be data a corerequested to read from the memory module.

At block 1604, the logic flow 1600 may include converting the datareceived via the high speed parallel link for communication via a highspeed serial link. For example, the memory interface may serialize thedata, via SerDes circuitry, to communicate the data via asingle/differential link. In embodiments, the SerDes circuitry mayconvert the data for communication via a high speed serial link usingany number of techniques, including but not limited to, a parallel clockSerDes technique, an Embedded clock SerDes technique, a 8b/10b SerDestechnique, and a bit interleaved SerDes technique. To convert the datafor serial communication, the SerDes circuitry may receive a parallelclock input, a set of data input lines (parallel link), and input datalatches. The SerDes circuitry may utilize a phase-locked looped tomultiply the incoming parallel clock up to a serial frequency for thehigh speed serial link. At block 1606, the logic flow 1600 may includesending the data via the high speed serial link to physical computeresources include the core requesting the data.

With respect to logic flow 1650, embodiments include receiving data viaa high speed serial link from a physical compute resources at block1652. In some instances, the data may be data a core requests to be readfrom the memory to be stored in the memory. The data may be communicatedto the memory interface via a memory interface of a sled having thephysical compute resources. In some instances, data may be received froma circuit switch coupled with the memory interface of the memoryexpander sled.

At block 1654, the logic flow 1650 may include converting the datareceived via high speed serial link for communication via a high speedparallel link. For example, the memory interface may deserialize thedata, via SerDes circuitry, to communicate the data via a parallel link.In embodiments, the SerDes circuitry may convert the data forcommunication via a high speed parallel link using any number oftechniques, including but not limited to, the parallel clock SerDestechnique, the Embedded clock SerDes technique, the 8b/10b SerDestechnique, and the bit interleaved SerDes technique. To convert the datafor parallel, the SerDes circuitry may utilize a receive clock output toclock down to a parallel data rate for communication of the data via theparallel link. The data may be communicated via a set of output linesusing output data latches to the memory based on the parallel rate, forexample. In some instances, a buffer (two registers) may be used toclock down the data from the high serial link to the parallel link rate.At block 1656, the logic flow 1600 may include sending the data via thehigh speed parallel link to memory or memory module.

FIG. 17 illustrates an embodiment of a logic flow 1700 that may berepresentative of some or all of the operations executed by one or moreembodiments described herein. For example, the logic flows 1700 and 1750may illustrate operations performed by a circuit switch. However,embodiments are not limited in this, and one or more operations may beperformed by other components or systems discussed herein.

The logic flow 1700, at block 1702, includes receiving configurationinformation to configure usage of memory, such as one or more memorymodules. In some instances, the configuration information may bereceived from a controller, such as baseboard management controller of asled, a rack management controller of a rack, and a pod managementcontroller of a pod. The configuration information may includeinformation associating workloads and cores processing the workloadswith particular memory modules. In some embodiments, the configurationinformation may include an indication of workload requirements and thecircuit switch may determine which memory modules may support theworkload. For example, the determination may be based on a storage size,a bandwidth, a transfer rate, error correction, and so forth for thememory module.

At block 1704, the logic flow 1700 may include determining aconfiguration of memory. Further and a block 1706, the logic flow mayinclude setting the configuration for the memory. The configuration mayinclude setting the circuit switch to direct read/write requests basedon data, associated workloads, and received addresses. For example, thecircuit switch may direct a read request to a particular memory andmemory module based on an address associated with the read request.

At decision block 1708, the logic flow 1700 may include determinewhether update configuration information is received. If so, the logicflow 1700 may include perform operations as previous discussed in blocks1704 and 1706. If not, the logic flow 1700 may include waiting a periodof time at block 1710 and then making the determination again atdecision block 1708.

The detailed disclosure now turns to providing examples that pertain tofurther embodiments. Examples one through twenty-five (1-25) providedbelow are intended to be exemplary and non-limiting.

In a first example, a system, a device, an apparatus, and so forth mayinclude a memory controller, and a memory interface coupled with thememory controller, the memory interface to receive data in parallel viaa bus, and convert the received parallel data to send to a memory moduleof a memory expander sled in serial via a high speed serial link, andreceive data in serial via the high speed serial link from the memorymodule of the memory expander sled, and convert the received serial datato send in parallel to the memory controller via the bus.

In a second example and in furtherance of the first example, a system, adevice, an apparatus, and so forth may include the memory interfacewherein the memory module is a dual in-line memory module or aintegrated circuit.

In a third example and in furtherance of any of the previous examples, asystem, a device, an apparatus, and so forth may include the memoryinterface comprising an optical transceiver and the high speed seriallink comprising an optical high speed serial link coupled with thememory module.

In a fourth example and in furtherance of any of the previous examples,a system, a device, an apparatus, and so forth may include the memoryinterface comprising an electrical transceiver and the high speed seriallink comprising an electrical high speed serial link coupled with thememory module.

In a fifth example and in furtherance of any of the previous examples, asystem, a device, an apparatus, and so forth may include the high speedserial link providing a memory channel for communication of data betweenthe memory controller and the memory module.

In a sixth example and in furtherance of any of the previous examples, asystem, a device, an apparatus, and so forth may include a plurality ofmemory controllers including the memory controller, and a plurality ofmemory interfaces including the memory interface, each of the pluralityof memory interfaces to couple to one of the plurality of memorycontrollers via buses, each of the plurality of memory interfaces tocouple with at least one of a plurality of memory modules including thememory module via at least one of a plurality of high speed serial linksincluding the high speed serial link.

In a seventh example and in furtherance of any of the previous examples,a system, a device, an apparatus, and so forth may include each of thehigh speed serial links to provide one of a plurality of memory channelsbetween one of the memory controllers and one of the memory modules.

In an eighth example and in furtherance of any of the previous examples,a system, a device, an apparatus, and so forth may include a processingunit comprising the plurality of memory controllers and the plurality ofmemory interfaces.

In a ninth example and in furtherance of any of the previous examples, asystem, a device, an apparatus, and so forth may include the memoryinterface to couple with one of a plurality memory modules including thememory module via a circuit switch coupled with the high speed seriallink.

In a tenth example and in furtherance of any of the previous examples, asystem, a device, an apparatus, and so forth may include the memoryinterface comprising serializer/deserializer (SERDES) circuitry toconvert data from parallel to serial and serial to parallel.

In an eleventh example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may include thememory interface comprising a pig tail connector comprising circuitry toconvert data from the parallel to serial and serial to parallel.

In a twelfth example and in furtherance of any of the previous examples,a system, a device, an apparatus, and so forth may include a memorymodule, and a memory interface coupled with the memory module. Thememory interface to receive data in parallel via a bus, and convert thereceived parallel data to send to to a memory module of a memoryexpander sled in serial via a high speed serial link, and receive datain serial via the high speed serial link from the memory module of thememory expander sled, and convert the received serial data to send inparallel to the memory controller via the bus.

In a thirteenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may include thememory interface comprising an optical transceiver and the high speedserial link comprising an optical high speed serial link coupled withthe memory controller.

In a fourteenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may include thememory interface comprising an electrical transceiver and the high speedserial link comprising an electrical high speed serial link coupled withthe memory controller.

In a fifteenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may include thehigh speed serial link providing a memory channel for communication ofdata between the memory controller and the memory module.

In a sixteenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may include aplurality of memory modules including the memory module, and a pluralityof memory interfaces including the memory interface, each of theplurality of memory interfaces to couple at least one of the pluralityof memory modules with one of a plurality of memory controllersincluding the memory controller via one of a plurality of high speedserial links including the high speed serial link.

In a seventeenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may includeeach of the high speed serial links to provide one of a plurality ofmemory channels between one of the memory controllers and one of thememory modules.

In an eighteenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth may include amemory expander sled comprising the plurality of memory modules and theplurality of memory interfaces.

In a nineteenth example and in furtherance of any of the previousexamples, a system, a device, an apparatus, and so forth the memoryinterface to couple the memory module with the memory controller via acircuit switch coupled with the high speed serial link.

In a twentieth example and in furtherance of any of the previousexamples, a method may include the memory interface comprisingserializer/deserializer (SERDES) circuitry to convert data received inparallel to send in serial to a memory controller, and convert datareceived in serial from the memory controller to parallel to send to thememory module.

In a twenty-first example and in furtherance of any of the previousexamples, a memory expander sled comprising the memory module in a lowpin count high speed memory slot, wherein the memory module is byteaccessible.

In a twenty-second example and in furtherance of any of the previousexamples, a method may include receiving data in parallel via a bus, andconvert the received parallel data to send to a memory module of amemory expander sled in serial via a high speed serial link, andreceiving data in serial via the high speed serial link from the memorymodule of the memory expander sled, and convert the received serial datato send in parallel to the memory controller via the bus.

In a twenty-third example and in furtherance of any of the previousexamples, a method may include receiving the data from a core inparallel via a high speed parallel link.

In a twenty-fourth example and in furtherance of any of the previousexamples, a method may sending the data in serial to the memory moduleof the memory expander sled via the high speed serial link.

In a twenty-fifth example and in furtherance of any of the previousexamples, a method may include wherein the high speed serial linkcomprising an optical high speed serial link coupling a memory interfacewith the memory module, the memory interface comprising an opticaltransceiver to send the data to the memory module; or the high speedserial link comprising an electrical high speed serial link coupling amemory interface with the memory module, the memory interface comprisingan electrical transceiver to send the data to the memory module.

Some embodiments may be described using the expression “one embodiment”or “an embodiment” along with their derivatives. These terms mean that aparticular feature, structure, or characteristic described in connectionwith the embodiment is included in at least one embodiment. Theappearances of the phrase “in one embodiment” in various places in thespecification are not necessarily all referring to the same embodiment.Further, some embodiments may be described using the expression“coupled” and “connected” along with their derivatives. These terms arenot necessarily intended as synonyms for each other. For example, someembodiments may be described using the terms “connected” and “coupled”to indicate that two or more elements are in direct physical orelectrical contact with each other. The term “coupled,” however, mayalso mean that two or more elements are not in direct contact with eachother, but yet still co-operate or interact with each other.

It is emphasized that the Abstract of the Disclosure is provided toallow a reader to quickly ascertain the nature of the technicaldisclosure. It is submitted with the understanding that it will not beused to interpret or limit the scope or meaning of the claims. Also, inthe preceding Detailed Description, it can be seen that various featuresare grouped together in a single embodiment for the purpose ofstreamlining the disclosure. This method of disclosure is not to beinterpreted as reflecting an intention that the claimed embodimentsrequire more features than are expressly recited in each claim. Rather,as the following claims reflect, inventive subject matter lies in lessthan all features of a single disclosed embodiment. Thus the followingclaims are at this moment incorporated into the Detailed Description,with each claim standing on its own as a separate embodiment. In theappended claims, the terms “including” and “in which” are used as theplain-English equivalents of the respective terms “comprising” and“wherein,” respectively. Moreover, the terms “first,” “second,” “third,”and so forth, are used merely as labels and are not intended to imposenumerical requirements on their objects.

What has been described above includes examples of the disclosedarchitecture. It is, of course, not possible to describe everyconceivable combination of components and methodologies, but one ofordinary skill in the art may recognize that many further combinationsand permutations are possible. Accordingly, the novel architecture isintended to embrace all such alterations, modifications, and variationsthat fall within the spirit and scope of the appended claims.

What is claimed is:
 1. An apparatus, comprising: a memory controller;and a memory interface coupled with the memory controller and a memorymodule, the memory interface to: receive data in parallel via a bus, andconvert the received parallel data to send to a memory module of amemory expander sled in serial via a high speed serial link; and receivedata in serial via the high speed serial link from the memory module ofthe memory expander sled, and convert the received serial data to sendin parallel to the memory controller via the bus.
 2. The apparatus ofclaim 1, wherein the memory module is a dual in-line memory module or aintegrated circuit.
 3. The apparatus of claim 1, the memory interfacecomprising an optical transceiver and the high speed serial linkcomprising an optical high speed serial link coupled with the memorymodule.
 4. The apparatus of claim 1, the memory interface comprising anelectrical transceiver and the high speed serial link comprising anelectrical high speed serial link coupled with the memory module.
 5. Theapparatus of claim 1, the high speed serial link providing a memorychannel for communication of data between the memory controller and thememory module.
 6. The apparatus of claim 1, comprising: a plurality ofmemory controllers including the memory controller; and a plurality ofmemory interfaces including the memory interface, each of the pluralityof memory interfaces to couple to one of the plurality of memorycontrollers via buses, each of the plurality of memory interfaces tocouple with at least one of a plurality of memory modules including thememory module via at least one of a plurality of high speed serial linksincluding the high speed serial link.
 7. The apparatus of claim 6, eachof the high speed serial links to provide one of a plurality of memorychannels between one of the memory controllers and one of the memorymodules.
 8. The apparatus of claim 6, comprising: a processing unitcomprising the plurality of memory controllers and the plurality ofmemory interfaces.
 9. The apparatus of claim 1, the memory interface tocouple with one of a plurality memory modules including the memorymodule via a circuit switch coupled with the high speed serial link. 10.The apparatus of claim 1, the memory interface comprisingserializer/deserializer (SERDES) circuitry to convert data from parallelto serial and serial to parallel.
 11. The apparatus of claim 1, thememory interface comprising a pig tail connector comprising circuitry toconvert data from the parallel to serial and serial to parallel.
 12. Anapparatus, comprising: a memory module; and a memory interface coupledwith the memory module, the memory interface to: receive data inparallel via a bus, and convert the received parallel data to send to toa memory module of a memory expander sled in serial via a high speedserial link; and receive data in serial via the high speed serial linkfrom the memory module of the memory expander sled, and convert thereceived serial data to send in parallel to a memory controller via thebus.
 13. The apparatus of claim 12, the memory interface comprising anoptical transceiver and the high speed serial link comprising an opticalhigh speed serial link coupled with the memory controller.
 14. Theapparatus of claim 12, the memory interface comprising an electricaltransceiver and the high speed serial link comprising an electrical highspeed serial link coupled with the memory controller.
 15. The apparatusof claim 12, the high speed serial link providing a memory channel forcommunication of data between the memory controller and the memorymodule.
 16. The apparatus of claim 12, comprising: a plurality of memorymodules including the memory module; and a plurality of memoryinterfaces including the memory interface, each of the plurality ofmemory interfaces to couple at least one of the plurality of memorymodules with one of a plurality of memory controllers including thememory controller via one of a plurality of high speed serial linksincluding the high speed serial link.
 17. The apparatus of claim 16,each of the high speed serial links to provide one of a plurality ofmemory channels between one of the memory controllers and one of thememory modules.
 18. The apparatus of claim 16, comprising: a memoryexpander sled comprising the plurality of memory modules and theplurality of memory interfaces.
 19. The apparatus of claim 12, thememory interface to couple the memory module with the memory controllervia a circuit switch coupled with the high speed serial link.
 20. Theapparatus of claim 12, the memory interface comprisingserializer/deserializer (SERDES) circuitry to convert data received inparallel to send in serial to a memory controller, and convert datareceived in serial from the memory controller to parallel to send to thememory module.
 21. The apparatus of claim 12, comprising: a memoryexpander sled comprising the memory module in a low pin count high speedmemory slot, wherein the memory module is byte accessible.
 22. Acomputer-implemented method, comprising: receiving data in parallel viaa bus, and convert the received parallel data to send to a memory moduleof a memory expander sled in serial via a high speed serial link; andreceiving data in serial via the high speed serial link from the memorymodule of the memory expander sled, and convert the received serial datato send in parallel to a memory controller via the bus.
 23. Thecomputer-implemented method of claim 22, comprising receiving the datafrom a core in parallel via a high speed parallel link.
 24. Thecomputer-implemented method of claim 22, comprising sending the data inserial to the memory module of the memory expander sled via the highspeed serial link.
 25. The computer-implemented method of claim 22, thehigh speed serial link comprising an optical high speed serial linkcoupling a memory interface with the memory module, the memory interfacecomprising an optical transceiver to send the data to the memory module;or the high speed serial link comprising an electrical high speed seriallink coupling a memory interface with the memory module, the memoryinterface comprising an electrical transceiver to send the data to thememory module.